With the increasing integration of ICs, chips can not provide an enough surface area to produce interconnects. Therefore, the multiple metal layers design rule is provided to produce interconnects of MOS transistors with narrowed-down line-width, especially in products with complex functions. For example, four or five metal layers used to connect devices are present in a microprocessor.
The multiple-interconnects are formed when the MOS is finished; therefore, the process for producing multiple-interconnects can be viewed as an independent semiconductor process. Among the multiple interconnects, the orientations of two independent interconnects are crossed-over each other; moreover, a dielectric layer isolating two independent interconnects is used to avoid shorts resulting from the contact of independent interconnects. The dielectric layer used to isolate interconnects is also known as the inter-metal dielectric (IMD) layer. In addition, the independent interconnects can be conducted by a traditional plug. As shown in FIG. 1A and FIG. 1B, a substrate 100 comprising a number off semiconductor devices was provided first. Then, a low-k insulating layer 110, i.e. a silicon oxide layer, was formed over the substrate 100. Subsequently, an interconnect 120 consisting of a plurality of metal lines isolated from each other was formed over the insulating layer 110 by a traditional metallization process. Then, another interconnect 130 consisting of a plurality of metal lines with an orientation crossing-over the interconnect 120 was formed over the insulating layer 130. By means of the method described above, the interconnects 120 and 140 were isolated by the low-k insulating layer 110.
The dielectric materials suitable for application in the isolation process as described above include silicon oxide (with a dielectric constant 4.about.5), TEOS (with a dielectric constant 4.about.5), silicon nitride (with a dielectric constant 6.about.9), silicon nitroxide, phosphorus silicon glass (PSG) and boron-phosphorus silicon glass (BPSG). During the 0.32 .mu.m process, the average dielectric constant of dielectric materials described above is about 4. In order to reduce the increasing RC-delay effect resulting from the narrowing distance between interconnects, it is necessary to develop a novel method for isolating the interconnects by using a low-k material (k&lt;3).